Mr. Stuart PEARCE
Senior Director Test 2.0 Solutions, AEM Holdings
Stuart is responsible for AEM semiconductor ATE and test instrumentation bringing disruptive and differentiated solutions to the semiconductor test space. Focusing on application specific test solutions, intelligent system level test and Advanced burn-in for semiconductor and electronics companies serving high performance computing, 5G, and AI markets.
With over 30 years’ experience in the capital test equipment industry Stuart has extensive experience defining, developing, and bringing to market test solutions that align with industry and customer requirements.
Prior to joining AEM Stuart held various senior management rolls at Thinfilm ASA as VP of Product management, bringing to market roll to roll printed electronics, Formfactor product engineering of advanced wafer test solutions, Credence ATE product line responsibilities, and Schlumberger ATE engineering, marketing and product line responsibilities. Stuart started in the UK as an engineer developing function and in-circuit board testers before his expatriate relocation to San Jose California to architect next generation test solutions with Schlumberger.
Presentation Title
Next-Gen Testing for AI and HPC: Embracing High Parallelism and Test 2.0 Innovations
Abstract
In the era of AI and HPC new test technologies have had to keep pace with the complexity and challenges of finding defects in these devices. The industry has embraced the need for system level test and high performance stress tests for these latest generation devices. The industry is now going through a paradigm shift to further optimize these new test flows and reduce the overall cost of test using massively parallel testers along with AI, ML and intelligent data management. We will share some of the concepts working with industry leaders bringing these latest AI and HPC chips to market.