Mr. Sebastiaan MULLER

Sebastiaan Muller is the Head of Business Development at Syenta, where he drives the adoption of a novel method of semiconductor manufacturing. With an extensive background from ASML, Sebastiaan specializes in bridging traditional lithography with next-generation Advanced Packaging and 3D integration strategies.

His international expertise is shaped by a foundation from Maastricht University and Lappeenranta University of Technology (LUT). At Syenta, he focuses on scaling, high-density interconnects and chiplet architectures across Europe, the US, and Asia.

Presentation Title

Scaling Panel Level Packaging with Localized Electrochemical Manufacturing

The performance of modern AI and high-performance computing (HPC) architectures is increasingly constrained by the ""memory wall,"" the growing disparity between GPU compute speed and HBM memory bandwidth. To sustain performance scaling, interconnect technologies must deliver higher data rates and increased line density without compromising manufacturability. This work presents a quantitative roadmap for copper interconnect scaling specifically optimized for Panel Level Packaging (PLP).

We review the evolution of copper-based redistribution layer (RDL) architectures, mapping achievable design points for large-format panels. Traditional PLP faces significant hurdles, including the inability to reach sub-2 µm line/space geometries without dual damascene processes and the mechanical challenges of panel warpage leading to incorrect patterning.

This presentation introduces Localized Electrochemical Manufacturing (LEM) as a definitive solution for scaling PLP:

Mechanical Compliance: LEM utilized adaptive stamps that conform to panel warpage, ensuring resolution and pattern uniformity across large areas.

High-Throughput Resolution: The technology combines the fine resolution of Laser Direct Imaging (LDI) with the throughput of a stepper, eliminating the need for complex stitching on 600mm panels.

Process Efficiency: By merging patterning and deposition into a single step, LEM simplifies the fabrication cycle, reducing major process steps from 18 in traditional semi-additive routes to just 12.

The analysis concludes that LEM-driven copper scaling provides an accelerated pathway to closing the compute-to-memory gap, extending the viability of Panel Level Packaging and conventional materials.

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