Mr. R. Selvakumar RAJAGOPAL
Senior Principal Engineer, DFX Architect, Intel Corporation
Selva is a Senior Principal Engineer and DFX Architect at Intel Technology Malaysia, bringing over 20 years of experience in SoC design engineering with deep specialization in Design-for-Test (DFT) and manufacturing. He plays a key role in defining test strategies for advanced chiplet and multi-die package architectures supporting Intel’s client product portfolio.
With a strong foundation in front-end DFT design, he has extensive experience translating complex design requirements into robust, scalable test architectures. He is instrumental in setting test coverage targets, driving defect-per-million (DPM) goals, and ensuring alignment between design intent and manufacturability.
He works closely with cross-functional teams, including manufacturing and foundry partners, to optimize yield, improve product quality, and accelerate time-to-market. His ability to bridge design and manufacturing domains enables seamless product realization from concept through high-volume production. He holds a Master’s degree in Engineering (Microelectronics) from Universiti Teknologi Malaysia.
Presentation Title
AI in DFT: From RTL Intent to Silicon Learning
The rapid growth in semiconductor complexity has fundamentally changed the nature of Design-for-Test (DFT). Modern systems-on-chip generate massive volumes of test, debug, and silicon data—far exceeding what traditional engineering approaches can effectively analyze. As a result, DFT is no longer a linear step in the design flow, but an interconnected lifecycle spanning RTL design, test generation, silicon validation, and yield learning.
This talk presents a lifecycle-centric view of DFT and explores how Artificial Intelligence (AI) is being applied across each stage—from front-end test intent generation and constraint validation, to ATPG optimization, and most impactfully, post-silicon debug and yield analysis. Real-world examples from industry and recent research highlight where AI is already delivering measurable value today.
Looking forward, the talk outlines a shift toward closed-loop, data-driven DFT systems, where insights from silicon continuously inform design and test decisions. This evolution signals a transition from static test flows to adaptive, learning-based systems.
The session concludes with key implications for DFT engineers, emphasizing the need to rethink methodologies, embrace data-centric approaches, and prepare for a future where test systems not only validate silicon, but continuously learn from it.