Mr. Ernest BLANCO
Systems Engineer, Cohu
Ernest Blanco is a Systems Engineer specializing in thermal and mechanical design for semiconductor final test. He develops and validates robust temperature control solutions that drive high yield, repeatability, and reliable system performance in production environments. With a strong system level mindset, Ernest integrates accurate thermal modeling, custom heater and heatsink design, precision mechanical design, thermal interface optimization, and control algorithms to solve complex temperature sensitive challenges.
He has 18 years of hands-on experience translating device level requirements into scalable, manufacturable solutions. Ernest is driven by transforming thermal constraints into competitive advantages through disciplined engineering, deep technical understanding, and practical system design.
Presentation Title
Controlling Temperature of High-Power AI Devices
Artificial intelligence devices have rapidly exceeded the 1 kW power level, redefining what is considered “high power” in semiconductor test environments. Prior to the A.I. era, 500 W represented a significant thermal challenge; power levels will soon exceed 4kW. Despite this shift, customers continue to demand tight temperature control during final test. Unlike data center or server environments, where avoiding over temperature is often sufficient, final test requires precise regulation to a specified setpoint under highly dynamic operating conditions.
This work presents a thermal control architecture optimized not only for steady state power dissipation, but also for fast dynamic response. Rather than maximizing heat removal alone, the design balances thermal resistance, thermal masses and control loop performance to achieve optimal overall behavior. In some cases, steady state dissipation capability is intentionally traded for improved transient response. The control system is tuned for near instantaneous reaction times on the order of one millisecond, with a strong emphasis on minimizing thermal stack up and thermal mass.
The proposed approach has successfully passed evaluation across multiple high power A.I. devices for multiple customers. Results demonstrate effective control of temperature overshoot and undershoot, maintaining compliance through aggressive power transients during test. This thermal architecture enables continued scaling of A.I. device performance while ensuring that final test does not become a limiting factor in an increasingly A.I. driven semiconductor roadmap.