Dr. James PAPANU

Dr. James Papanu is Senior Director for 3DI Technology at Tokyo Electron Kyushu and is jointly affiliated with TEL’s Corporate Innovation Division and Technology Center of America and. He has over 35 years of experience in the semiconductor industry, specializing in packaging, wafer fabrication, and PV/glass coating. He currently oversees the development of technologies and toolsets for fusion and hybrid bonding, including die-to-wafer bonding. Prior to joining TEL in 2022, Dr. Papanu was Technology Director for Advanced Packaging at Applied Materials where he led development in die singulation and cluster tool integration. His leadership resulted in successful qualification of new toolsets for high-volume production, covering the entire product lifecycle from initial concept to customer engagement and product release. Prior to Applied Materials, he was at Lam Research and Philips Semiconductors. Dr. Papanu received his Ph.D. in Chemical Engineering from UC Berkeley, and has been awarded over 60 patents in plasma and wet processing, advanced packaging, and chamber technologies.

Presentation Title

Key APHI Enablers to Sustain the AI/HPC Juggernaut: Bonding, Test and Metrology

High Performance Computing (HPC) and Artificial Intelligence (AI) - both separately and jointly since AI is reliant on HPC - are the primary drivers for advanced chipsets and innovative semiconductor manufacturing, including Heterogenous Integration and Advanced Packaging (AP). As part of the overall ecosystem, die-to-wafer (D2W) and wafer-to-wafer (W2W) fusion and hybrid bonding, electrical test, and metrology must keep up with the demands posed by AI and HPC roadmaps. At the component level, HPC and AI are critically dependent on next generation XPUs and High Bandwidth Memory (HBM), and new advanced memory concepts are also being explored. Advanced bonding hardware and processes must accommodate high levels of die and/or wafer warpage, large die (~900 mm2) die of varying aspect ratios, and stacking of thin (~30 um) wafers and/or die. These die and wafers must be bonded with low levels of distortion to meet hybrid and fusion bonding specifications applicable to AP and front-back-side power delivery networks and complimentary field effect transistor applications. And these bonding steps must be performed with sufficiently high throughput to provide a viable cost of ownership for customers.

Furthermore, significant challenges arise with respect to device testing, where “device” is no longer simple and must now be defined in terms of die, die stacks, and interposer modules. Also, to support development and volume production of next-generation devices and packages, and to understand/correlate interrelationships of bonding and electrical yield, advanced metrology/inspection capability is needed at both the component-level (e.g. HBM die stacks) and package level. In this paper, the focus will be on bonding and electrical test technologies and tools, which are core product offerings in the TEL 3DI and Test portfolio. Also, several important needs/gaps for metrology will be highlighted as opportunities for innovative solutions.

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