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[Webinar] Advanced Packaging Forum Speakers' Biography and Abstracts

[Webinar] Advanced Packaging Forum Speakers' Biography and Abstracts

 

Moderator:
Mr. Albert LAN
Senior Global Packaging Technical Director
Applied Materials Taiwan Ltd
Taiwan

Mr. Albert Lan joined Applied Materials in 2017 as Senior Global Packaging Technical Director. In this capacity, Mr. Lan works closely with customers on advanced wafer-level packaging technology development from process integration points of view including fan-out, 2.5D/3D TSV, System in Package (SiP), and CoW/WoW copper hybrid bonding.

Mr. Lan brings with him over 25 years of experience in the semiconductor industry, focused on advanced wafer-level packaging technologies. Before joining Applied Materials, he served as the Head of Engineering Center at Siliconware Precision Industries (SPIL), one of the top three largest assembly houses in the world, for 13 years and at Amkor Taiwan for 6 years.


Mr. Sanggaran SUBRAMANIAM
Equipment Manager, Assembly Operations
United Test and Assembly Center Ltd (UTAC)
Singapore

Sanggaran, joined UTAC Singapore in Dec 2015 and is currently the Manager of Equipment Engineering for WLP Assy Operation. He has over 20 year’s extensive experience in Backend Assy Operation. Prior to joining UTAC, he worked in Fairchild Semiconductor Malaysia, ST Microelectronic Malaysia and Hitachi Semiconductor Malaysia.

In his capacity as Manager of Equipment Engineering, he successful deployed # of automation projects, productivity improvement and remarkable cost saving projects to support the COGS improvement. He build strong technical team and cross functional to drive Smart Manufacturing approach. He provide Equipment Engineering Solution for WLP equipment’s such as Taper, Grinder, Laminator, Mounter, Detaper, laser Saw, Mechanical Sawing, AOI , Tape &Reel .Proven ability to drive excellent result with short and long term solution; Go to person for Uptime, MTBA, Cost, Quality improvement and Equipment Engineering improvement.

Sanggaran earned his Diploma in Electronics Communication System and his Bachelor of Engineering in Electronic System Design Engineering from University of Northumbria in Malaysia.

Presentation Title
Remote Equipment Control Centre (RECC) Approach for Smart Manufacturing and Productivity Improvement

This paper presents the potential of RECC on cost savings and productivity improvement through maximizing machines’ performance with less human resources in a dynamic manufacturing environment with an assortment of different makes and types of machines. Such assortment of machines are integrated into the RECC which monitors and collects real time equipment parameters and performance, then pushes vital reports and alarms to users at a centralized dashboard for expeditious corrective actions and effective management of equipment utilization. Reduction of equipment downtime and headcount savings are achieved through remote alarms assist, automated machines parameters surveillance and tweaking with strict password control to allow access only to authorized personnel.


Mr. Chan Pin CHONG
Executive Vice President & General Manager, Products & Solutions
Kulicke & Soffa Pte Ltd
Singapore

Chan Pin was appointed as Executive Vice President & General Manager, K&S' Products and Solutions in December, 2019.

He joined K&S in 2014 as Vice President of Wedge Bonders business unit and has successfully turnaround the business and led the team to higher growth by diversifying the business into the battery bonding market.

Chan Pin is a technology industry veteran with more than 24 years of engineering and operations experience in the semiconductor and electronics industry. He started his career first as a Process and Test Engineer at Motorola Pagers and Cellular group and pioneered multiple factories in Asia before advancing to the role of Manufacturing Manager at Flextronics. In 1999, Chan Pin joined KLA-Tencor and held a number of diverse positions, including Senior Technical Director of Engineering and General Manager of Strategic Business Unit in Greater China. Chan Pin then pioneered the efforts of starting the MEMS factory in Singapore when he became the Vice President of Sales and General Manager at Form Factor. Most recently, he was the Global President & CEO at Everett Charles Technologies, managing and leading in test and probe technologies.

Chan Pin received his bachelor's degree in Electrical Engineering and Computer Science from the State University of New York at Buffalo and a master's degree in Business Administration from the University of Leicester, United Kingdom.

Presentation Title
Challenges in Placement Requirements for Heterogeneous Integration

The growth of advance packaging especially with Heterogeneous integration and 3D stacking, starting with EMIB (Embedded Multi-die Interconnect Bridge), inFO and CoWoS (Chip-on-Wafer-on-Substrate) ,Foveros, SoIC (System-on-Integrated Chips) and (3D MUlti-STack) technologies, are emerging as a more cost-efficient way to achieve greater integration and IO densities. With this trend of heterogeneous integration, we can overcome Moore’s law and the reliance of few key logic companies with fab capabilities below 7nm or fine pitch packaging.  This presentation will discuss the impact of these technologies and requirements on advance backend packaging such as on Flip chip(FC), backend lithography and Thermo compression bonding (TCB) equipment and how challenges are being addressed.


Mr. Chee Ping LEE
Senior Technologist and Technical Marketing Manager
Lam Research
Singapore

Lee Chee Ping is the Senior Technologist and Technical Marketing Manager for Lam Research, focusing on the advanced packaging segment. He has >16 years of semiconductor industry experience in thin-film deposition processes, supporting customers across Asia.

Over the last 10 years, he has built in-depth knowledge and experience in the advanced packaging / heterogeneous integration market and technology. He began with process management role, developing OSAT process support teams in Asia region and now, includes advanced packaging product marketing.

Lee Chee Ping received his M.Eng in Technology Management from the University of South Australia, as well as both M.Sc in Financial Engineering and B.Eng in Chemical Engineering from National University of Singapore.

Presentation Title
Innovative, Market Leading Solutions for Heterogeneous Integration
Heterogenous integration is about bringing multiple chips together into a single package. While conceptually very similar to multi-chip modules, recent development involves strategy of using advanced wafer manufacturing technologies to meet the ever-increasing performance and form factor requirements. This presentation will talk about the market and technology trends in heterogenous integration. It will follow with overview of the various market leading equipment solutions that Lam has developed to enable heterogeneous integration by our customers.


Mr. Ravichander RAO
Product Marketing Manager
KLA Corporation
India

Ravi is Product Marketing Manager with KLA. He is responsible for marketing in advanced wafer level packaging. Ravi has 15 years of experience in product development and marketing. He holds Master of Science from the Ohio State University, USA and MBA from SP Jain School of Global Management, Singapore.

Presentation Title
Inspection Challenges in 3D Stacking

Defectivity, wafer shape and overlay controls are critical for achieving higher yields in 3D stacking. More inspection and metrology are required for controlling these parameters. The presentation will discuss inspection challenges in 3D Stacking.


Mr. Hoi Ping, Eric NG
Senior Business Development
ASM Pacific Technology
Hong Kong

Eric NG, has been in business development position at ASMPT for over 6 years, with responsibility of product marketing and development in advanced packaging technology. His main responsible area includes advanced interconnect business such as flip chip bonding, TCB bonding, Fan-out wafer and panel level packaging.

Prior to join ASMPT, Eric was in engineering position for product development in semiconductor industry. Over his previous more than 15 years’ experience, Eric spent time doing process and product R&D including FPC (flexible printed circuit), package assembly and thermal cooling solution for package device.

Eric received his Bachelor and Master degree in Mechanical Engineering field from Hong Kong University of Science and Technology.

Presentation Title
From 2.5D to 3D Heterogeneous Integration and its Process Challenges and Packaging Solution

We are entering into a future world of Artificial Intelligence (“AI”). Massive and high speed data transfer by 5G connection and super High Performance Computing (HPC) for both end-terminals and also edge computing are the key enabler to turns AI on. The design and assembly of HPC chips is then the critical process steps for our industry to address so as the bright AI enabled future for our societies can be realized.
Moore’s Law which has guided the semiconductor industry for decades, was being realized that no longer effective to continue. In order to reduce the financial commitment for future node development, an effective approach is switching from “only front-end node scaling” to “combination with back-end scaling”. Heterogeneous Integration (HI) is the way forward. HI is a backend approach by means of advanced packaging technologies which enable the integration of multiple chiplet, with different functionalities and each fabricated with best fit node in terms of technology and economic, to reassemble an SoC (System on Chip) like function.

There are different HI approaches. Some of them are already in volume production mode. Based on the package configuration and nature, there can be identified with 3 different type, which are 2.5D Interposer Approach (such as CoWoS), Embedded Bridge Approach (such as EMIB), and Heterogeneous integrated Fan-Out (HIFO Approach (such as FoCoS, InFOoS).

There exists many well-known process approaches for heterogeneous integration, which can be classified into package level and chip level. In package level HI, such as the 2.5D ways with CoWoS, EMIB and HIFO (Fan-out (FO) base 2.5D package integration). On the other hand, chip level integration such as FOVEROS and SoIC even further extend the “Chiplet” concept. In which it makes use of advanced interconnect technology (including MRFC, TCB, hybrid bond…etc) to achieve the purpose of heterogeneous integration.

Besides package level integration, 3D IC integration approach is being advocated in order to achieve the next level of integration with direct chip to chip interconnection without any external interposer or RDL routing. 3D IC with copper to copper joint formation is based on a hybrid bonding process which is to push the envelope for the development of backend equipment and processing technology (for example for the die placement accuracy).

In this presentation, process challenges and the corresponding solution including manufacturing equipment solution will be discussed for different heterogeneous integration approaches, including the 3D IC integration.


Dr. Dave THOMAS
Vice President, Product Management
SPTS Technologies Ltd
United Kingdom

Dr Thomas worked for Philips Components and Nortel before joining SPTS (at that time Electrotech) in 1994 as a PVD Process Engineer, becoming PVD Technology Manager for Japan in 1996.

He became Product Marketing Manager for Etch Products in 1997 and promoted to Marketing Director for Etch Products in 2008, responsible for SPTS’s etch product line, including marketing, product positioning & sales support. In 2020, he was promoted to VP of Product Management, expanding his role to cover all SPTS plasma etch and deposition products.

Dr. Thomas holds a BSc in Chemistry (Leeds University), MSc in Surface Chemistry & PhD Plasma Etching & Deposition (University of Bristol), and actively participates, and presents widely on etch and deposition technologies at global conferences. He has also authored over 30 technical articles and papers.

Presentation Title
Blanket Silicon Etching Processes for Advanced Packaging Applications including Via Reveal, Extreme Thinning, FO-WLP and Post-Grind Smoothing

Blanket Si etching on 300mm wafers is a critical process for a range of advanced packaging technologies. One method of 3D stacking involves exposing via-middle TSVs from the back-side of device wafers by combining mechanical grinding, CMP and dry etching to a depth of 10-20µm. High rate etching is required but high precision is also needed to control within wafer uniformity, selectivity to thin TSV liners and smoothness of post-etch surfaces. Incoming Si thickness variations make end-point detection essential for wafer to wafer process control. The Si dry etching can also be extended and tuned to smooth out the roughness from the grinding step thereby eliminating the requirement for costly CMP. A second method of 3D stacking involves face to face bonding of device wafers plus a combination of grinding/CMP and then dry etching of ~50µm of Si to leave 5µm of the top wafer. Then via-last TSVs are etched through the remaining thin Si to form the wafer to wafer connections. End-point detection for the Si etching is key in controlling the wafer to wafer TSV depth. In a further iteration of this scheme a combination of dry/wet Si etching and the use of a SiGe etch-stop layer allows the final top Si thickness to be as low as 0.5µm. A third packaging method involves FO-WLP where the multi-layer interconnect from one wafer is transferred onto a FO layer with embedded die. Here the Si donor wafer is etched completely away to leave only the interconnections on the recipient FO wafer.

Examples of Si etching for Via Reveal, extreme thinning and FO-WLP will be presented. The requirements and characteristics of the etch processes will be described along with the corresponding end-point detection methods.


Mr. Nir SEVER
Senior Director of Product Marketing
proteanTecs
Israel

Nir Sever is an industry veteran with over 30 years of technological and managerial experience in advanced VLSI engineering. Before joining proteanTecs, Nir served for 10 years as the COO of Tehuti Networks, a pioneer in the area of high-speed networking Semiconductors. Prior to that, he served for 9 years as Senior Director of VLSI Design and Technologies for Zoran Corporation, a recognized world leader in Semiconductors for the highly competitive Consumer Electronics market. Nir was responsible for driving Zoran’s silicon technologies and delivering more than 10 new silicon products each year. Prior to that, Nir held various managerial and technological VLSI roles at 3dfx Interactive, GigaPixel Corporation, Cadence Design Systems, ASP Solutions, and Zoran Microelectronics. Nir holds a B.Sc in Electrical Engineering from The Israel Institute of Technology, Technion.

Presentation Title
Deep Data Chip Telemetry for Quality & Reliability Monitoring of Heterogeneous Packaging

Advanced packaging solutions are a key pillar in overcoming the existing limitations of monolithic integration, which has become more difficult and expensive at each node. Heterogeneous integration technologies, such as 2.5D/3D stacking, tiling, intra-die routing, through-silicon vias, chiplets and fan-out, have and significantly increased system capabilities and performance but have introduced new challenges to an industry accustomed to a “Moore’s Law inter-die scaling” approach. Quality and reliability are increasingly harder to achieve due to an inherent high density and high frequency nature, with limited visibility after assembly.

In this presentation, a new concept based on Deep Data chip telemetry will be introduced, offering a unique combination of embedded IPs (Agents), both core and I/O, and a software platform that implements machine learning algorithms and data analytics. Higher visibility for data-driven decision making is achieved, in production and when deployed in the field. Findings from a 7nm HBM ASIC controller use case will be presented.

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